The present invention relates to a current driver circuit, and more particularly, to a current driver circuit that is optimal for a write coil driver of, for example, a hard disk drive (HDD) device.
In a current driver circuit, when driver switching is performed, the load of the current driver circuit or the inductive load (coil component) included in the line between the driver circuit and the load results in the generation of a flyback voltage. The flyback voltage causes overshooting and ringing of the output current. To prevent or decrease overshooting and ringing, a damping circuit is included in the current driver circuit. The switching speed of the current driver circuit has become faster. Accordingly, there is a demand for a damping circuit that smoothes the output waveform of the current driver circuit without decreasing the switching speed of the current driver circuit.
FIG. 1 is a schematic circuit diagram showing a first example of a prior art current driver circuit for driving a write magnetic head of an HDD device. The current driver circuit 50 includes a pair of drive sections (inverter circuits) 51, 52. A load circuit 53 formed by a write coil (the write magnetic head) is connected between an output terminal 51a of the first drive section 51 and an output terminal 52a of the second drive section 52.
When recording data on a track of a magnetic disk via the write magnetic head, a first input signal Vi1 is provided to an input terminal 51b of the first drive section 51. A second input signal Vi2 is provided to an input terminal 52b of the second drive section 52. As shown in FIG. 2, the first and second input signals Vi1, Vi2 are complementary. When one of the signals Vi1, Vi2 has a positive high potential voltage (high level), the other one of the signals Vi1, Vi2 has a low potential voltage (low level).
When the first input signal Vi1 is low and the second input signal Vi2 is high, an output voltage Vo1 from the first drive section 51 has a high potential, and an output voltage Vo2 from the second drive section 52 has low potential. Accordingly, an output current Io flows from the first drive section 51 to the second drive section 52 in the load circuit 53.
On the other hand, when the first input signal Vi1 is high and the second input signal Vi2 is low, the output voltage Vo2 from the second drive section 52 has a high potential, and the output voltage Vo1 from the first drive section 51 has low potential. Accordingly, the output current Io flows from the second drive section 52 to the first drive section 51. The direction of the output current Io flowing through the load circuit 53 changes the magnetized direction of the magnetic disk and records data on the track.
The load circuit 53 includes an inductive impedance (reactance) component. Thus, a flyback voltage is generated at the output terminals 51a, 52a when the current driver circuit 50 performs switching (when the levels of the first and second input signals Vi1, Vi2 are shifted). As shown in FIG. 2, the flyback voltage results in the occurrence of overshooting and undershooting in the waveform of the output current Io flowing through the load circuit 53. Further, since the capacitance, resistance, and impedance components of the inductance in the current driver circuit 50, the load circuit 53, and the line cause ringing, a smooth current waveform cannot be obtained.
A damping circuit 55 is thus provided in the current driver circuit 50. The damping circuit 55 includes a capacitance C1 and a resistor R1 connected in series between the output terminals 51a and 52a. The differential voltage (Vo1-Vo2) between the output terminals 51a, 52a changes in accordance with a frequency determined by a time constant corresponding to the capacitance C1 and the resistor R1. In such state, only the high frequency components of the differential voltage are bypassed via the damping circuit 55 to shape the output current Io flowing through the load circuit 53.
However, in the damping circuit 55 of FIG. 1, when the differential voltage between the output terminals 51a, 52a fluctuates, the frequency of the fluctuation activates the is damping circuit 55 and rounds the waveform of the output current Io. This hinders high speed switching operation. Thus, the setting of the damping frequency becomes especially difficult when the switching speed increases.
FIG. 3 is a schematic circuit diagram showing a second example of a prior art current driver circuit 60. The current driver circuit 60 includes a first damping circuit 56A having a pair of resistors R2 connected to the output terminal 51a, and a second damping circuit 56B having a pair of resistors R2 connected to the output terminal 52a. The output terminals 51a, 52a are each connected to a positive power supply and the ground by the associated pair of resistors R2. The resistors R2 have a relatively low resistance, and the output terminals 51a, 52a are terminated with a relatively low impedance. Accordingly, the occurrence of ringing in the output current Io flowing through the load circuit 53 is inhibited.
In the damping circuits 56A, 56B of FIG. 3, the output terminals 51a, 52a are connected to the positive power supply and the ground by the associated pair of resistors R2. The output current Io thus constantly flows through the damping circuits 56A, 56B, which causes a large power loss.
FIG. 4 is a schematic circuit diagram showing a third example of a prior art current driver circuit 70. The current driver circuit 70 includes a first damping circuit 57A having a series-connected circuit formed by a plurality of diodes D3 and a resistor R3, and connected to the output terminal 51a, and a second damping circuit 57B having a series-connected circuit formed by a plurality of diodes D3 and a resistor R3, and connected to the output terminal 52a. The damping circuits 57A, 57B are each activated when the flyback voltage causes the associated output voltages Vo1, Vo2 to be less than a predetermined voltage. The activation restricts the output current Io and thus decreases the overshooting of the current waveform and shapes the waveform of the output current Io flowing through the load circuit 53.
Since the damping circuits 57A, 57B of FIG. 4 are activated by the waveform of the flyback voltage, the power loss is small. However, the ON voltage of the damping circuits 57A, 57B must be set so that damping is performed when the damping circuits 57A, 57B are activated. Further, it is difficult to perform damping efficiently within the minimum period of time. Thus, it is difficult to perform waveform shaping at a high speed during high speed switching operations.
It is an object of the present invention to provide a current driver circuit that smoothly controls the output current waveform while achieving a high switching speed.
To achieve the above object, the present invention provides a current driver circuit for receiving an input signal and current driving a load. The current driver circuit includes a drive circuit for supplying the load with current. A damping circuit is connected to the drive circuit for restricting the current supplied to the load from the drive circuit in accordance with a pulse signal. A damping control circuit is connected to the damping circuit for generating the pulse signal in response to the input signal and providing the pulse signal to the damping circuit.
A further aspect of the present invention provides a differential current driver circuit for receiving first and second input signals and current driving a load. The differential current driver circuit includes a first drive circuit for supplying the load with a first current. A first damping circuit is connected to the first drive circuit for restricting the first current supplied to the load from the first drive circuit in accordance with a first pulse signal. A first damping control circuit is connected to the first damping circuit for generating the first pulse signal in response to the first input signal and providing the first pulse signal to the first damping circuit. A second drive circuit supplies the load with a second current. A second damping circuit is connected to the second drive circuit for restricting the second current supplied to the load from the second drive circuit in accordance with a second pulse signal. A second damping control circuit is connected to the second damping circuit for generating the second pulse signal in response to the second input signal and providing the second pulse signal to the second damping circuit.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.